1. Field of the Invention
The invention relates to a fabrication method for a single-electron transistor (SET), and more particularly to a single-electron transistor with self-aligned sidewall spacer gates.
2. Description of the Related Art
As semiconductor technology continuously progresses toward a deep sub-micron regime, namely a nanometer scale regime, there has been a tremendous tendency to increase the integration densities of IC devices and decreasing the scale thereof. In general, the fabrication methods for a nanoscale device include an epitaxial growth technique, a self-assembly technology and a lithography process. The epitaxial growth technique is most suitable for III-V group compound semiconductor applications. The self-assembly technology using a natural rule of grain growth can form nano-size grains, but cannot control grain growth on a specific location and the amount of the grown grains. The lithography process has limitations in the apparatus light source, such that a poor resolution cannot fulfill requests for the width of a nanowire in a nano-level quantum device.
Choi et al. disclose “Fabrication of a dual-gate-controlled Coulomb blockade transistor based on a silicon-on-insulator structure” in 1998 Semicond. Sci. Technol. Electron-beam lithography has been employed to fabricate a gate-controlled single-electron transistor, but has disadvantages as follows. First, the electron-beam lithography has a proximity effect upon two separated under-gate patterns resulting in excess distance therebetween, reaching approximately 100 nm, thus the quantum well capacitor for storing charges is large and the single-electron effect is only measured at an extremely low temperature of about 15 mK. Second, use of electron-beam lithography and etching on the two separated under-gate patterns easily causes an asymmetric structure, resulting in some loss of electrical performance.